Reference is made to FIG. 1, which is a schematic view illustrating a conventional multi-phase brushless DC motor driving circuit. When the conventional multi-phase brushless DC motor driving circuit drives a brushless direct current (BLDC) motor, the multi-phase brushless DC motor will detect a current location of a rotor (e.g., a coil Cu, a coil Cv and a coil Cw). Then, a micro control unit (MCU) 3 controls a pulse width modulation (PWM) generator 2 according to a motor speed signal and a detecting signal, which represents the current location of the coil Cu, the coil Cv and the coil Cw, to generate PWM signals u-w and x-z to control the conducting and cutting off of a plurality of high-side transistors U-W and low-side transistors X-Z in a driving-stage circuit 1.
Considering that a converting time exists when the transistor is converted from a conductive state to a cut off state or from a cut off state to a conductive state, in order to prevent the high-side transistors U-W and the low-side transistors X-Z from being conducted at the same time, which may cause circuits to burn out, the PWM signals u-w of the high-side transistors U-W and the PWM signals x-z of the low-side transistors X-Z are complementary signals, and the transition edges in the PWM signals u-w of the high-side transistors U-W and in the PWM signals x-z of the low-side transistors X-Z are delayed for a period of time when generating the PWM signals u-w and x-z to control the high-side transistors U-W and the low-side transistors X-Z. Generally, the delay time is called dead time.
Reference is made to FIG. 2A and FIG. 2B, which are waveform views of the conventional multi-phase brushless DC motor driving circuit.
As shown in FIG. 2A, the rising edges in the PWM signal u and the PWM signal x for the high-side transistor U and the low-side transistor X are respectively delayed for a period of time Td to alternately conduct the high-side transistor U and the low-side transistor X. When the multi-phase brushless DC motor MT is driven, during the time when the current flows from the multi-phase brushless DC motor MT to the node UO, the voltage VUO of the node UO is shown in FIG. 2A (in which the threshold voltage of a body diode of the low-side transistor X is Vd, and the supply voltage of the driving-stage circuit 1 is VDD, details of which are omitted herein). In other words, as also shown in FIG. 2B, the rising edges in the PWM signal u and the PWM signal w for the high-side transistor U and the low-side transistor W respectively are delayed for the period of time Td to alternately conduct the high-side transistor U and the low-side transistor X. When the multi-phase brushless DC motor MT is driven, during the time when the current flows from the node UO to the multi-phase brushless DC motor MT, the voltage VUO of the node UO is shown in FIG. 2B (in which the threshold voltage of a body diode of the low-side transistor X is Vd, and the supply voltage of the driving-stage circuit 1 is VDD, details of which are omitted herein).
Assuming that the cycle of the non-adjustment PWM signal is T and the time of a high potential is Ton, according to the voltage VUO of the node UO in FIG. 2A, when the multi-phase brushless DC motor MT is driven, during the time when the current flows from the node UO to the multi-phase brushless DC motor MT, an equivalent duty cycle of the driving-stage circuit would be (Ton-Td)/T. In addition, according to the voltage VUO of the node UO in FIG. 2B, when the multi-phase brushless DC motor MT is driven, during the time when the current flows from the multi-phase brushless DC motor MT to the node UO, the equivalent duty cycle of the driving-stage circuit is (Ton+Td)/T.
Since the PWM signal u and the PWM signal w provided for the high-side transistor U and the low-side transistor W are complementary signals, if the duty cycle of the high-side transistor U is D % (i.e., Ton/T in FIG. 2A), the duty cycle of the low-side transistor W would be (100−D) % (i.e., Ton/T in FIG. 2B). Therefore, when the multi-phase brushless DC motor MT is driven, the overall equivalent duty cycle of the driving-stage circuit would be (D %−Td %)−[(100−D) %+Td %], which is equal to (2D−100−2Td) %.
Accordingly, by delaying the transition edges of the PWM signals of the high-side transistor and the low-side transistor for a period of time, even though the situation that the high-side transistor and the low-side transistor in the driving-stage circuit are conducted at the same time can be prevented, the overall equivalent duty cycle of the driving-stage circuit will be shortened due to the delay time so that the operation efficiency of the motor is reduced.